Role: Design Verification Engineer
Location: Santa Clara, CA (onsite)
Duration: 12 contract
Job Description:
We are seeking a seasoned verification lead with expertise or significant interest in IO/PHY verification. You have had significant success driving IP verification, UVM and SystemVerilog. This senior role will stretch you as you lead DV teams in new directions, network with our world-class design/DV teams.
THE PERSON:
You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.
KEY RESPONSIBILITIES:
• Define verification plan, and provide technical direction to execution teams
• Comprehend AMS, Firmware and design spec. Work with other functional leads to come up with a DV plan and execute the plan.
• Create UVM/SystemVerilog based testbenches and tests.
• Make sure that design is bug free.
• Lead Formal verification.
• Support Post-Si teams for Product Performance, Power and functional issues debug/resolution
PREFERRED EXPERIENCE:
• IO/PHY knowledge.
• Formal verification expertise.
• Firmware experience.
• Excellent communication, management, and presentation skills.
• Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies
ACADEMIC CREDENTIALS:
• Bachelor’s or Master’s degree in related discipline preferred
